In the conventional semiconductor memory device, as in the construction shown in FIG. 1, for example, an external address signal Add is input to a row decoder 8 and a column decoder 9 as respective row address signal AD1 and column address signal AD2, through an address register 7. Respective decoders produce decode signals based on respective address signals to select a memory cell of the corresponding address in a memory cell array 1, and writing and reading of data is performed.
In this case, the address register 7 receives an activation signal CS from a chip activation register 4 to control the transmission of the address signal ADD for the internal circuit. The activation signal CS is generated, when reference is made to the construction in FIG. 3, by a chip activation register on the basis of a chip selection signal CSX of an active row, the chip selection signal of which is supplied externally. In this case, the chip selection signal CSX is input to a latch circuit 30 formed by two inverters 34 and 35 connected in a reverse parallel relationship, through two stage inverters 31 and 32 and a transfer gate 33, and is further output as the activation signal CS through two stage inverters 36 and 37. In this construction, when the chip selection signal CSX is "H" level, an "H" level signal is input to the latch circuit 30 and a "L" level signal is output from the latch circuit 30. Therefore, the activation circuit CS becomes "L" level to maintain the address register 7 in an inactive state. Conversely, when the chip selection signal CSX is "L" level, since a "H" level signal is output from the latch circuit 30, the activation signal CS becomes "H" level to activate the address register 7.
On the other hand, for one of the inverter 34 of the latch circuit, a power source voltage Vout is supplied from an initialization setting circuit 20a which will be discussed later (see FIG. 3). For the other inverter 35, power source voltage Vcc is directly supplied from a high potential power source line (not shown) similarly to other circuits. Upon ON set of power (Vcc) supply for such semiconductor memory device, by an operation of the initialization setting circuit 20a, the power source voltage Vout is supplied to the inverter 34 with a delay from the supply of the power source voltage Vcc for the inverter 35. Therefore, upon ON-set of the power supply, because of the operation of the inverter 35 in advance of initiation of the operation of the inverter 34 in the latch circuit 30, the potential at the input terminal A of the latch circuit 30 becomes "H" level, and by this operation of the inverter 35, the output signal of the latch circuit 30 is latched at "H" level after the power supply for the inverter 34.
FIG. 2 shows one example of construction of the above-mentioned initialization setting circuit 20a.
In this figure, for the input terminal of a CMOS inventer 21 (p channel transistor TR3 and n channel transistor TR4), the source of an n channel transistor TR1 is connected. The drain and the gate of the n channel transistor TR1 are connected to a high potential power source line Vcc. On the other hand, to the input terminal of the inverter 21, the drain of a p channel transistor TR2 is connected, which has the source connected to the power source line Vcc, and the gate connected to the output terminal of the inverter 21. Further, a resistor R is disposed between the input terminal of the inverter 21 and a low potential power source line Vss. On the other hand, the output terminal of the inverter 21 is output to the gas of a p channel transistor TR5, the transistor of which has the source connected to the power source line Vcc, and the drain connected to the output terminal (output voltage Vout) of the initialization setting circuit 20a.
When the power source Vcc is allied to the initialization circuit 20a constructed as set forth above, a voltage lower than the power source voltage Vcc by a magnitude corresponding to the threshold level (VthN) of the transistor TR1, is applied to the input terminal of the inverter 21. Subsequently, after a given period from the rise of the power source voltage Vcc, the inverter 21 makes a decision for "H" level for the level of (Vcc-VthN) to output a "L" level output signal to the transistor TR5. By this, the transistor TR5 is turned ON to output the output signal Vout equal to the power source voltage Vcc at the output terminal. On the other hand, at the same time, the transistor TR2 is turned ON to maintain the level at the input terminal of the inverter 21 at "H" level.
Accordingly, the initialization setting circuit 20a is responsive to ON-set of the power supply voltage Vcc and outputs the output signal Vout more rapidly than the power source voltage Vcc at the output terminal with a given period of delay from ON-set. Through the operation set forth above, the power supply for the inverter 34 of the latch circuit 30 is slightly delayed.
However, in the initialization setting circuit 20a as set forth above, a problem will be arise when power source voltage Vcc is shut down at the condition in which the voltage Vout is supplied to the inverter 34 of the latch circuit 30 from the output terminal by ON-set of the power supply (namely, the condition that the signal line connected to the drain of the transistor TR5 is charged at a level substantially corresponding to the power source voltage Vcc).
Namely, the charge accumulated at the output terminal cannot be discharged, and as a result, the voltage level (level of the output signal Vout) at the output terminal is floating at an intermediate level. Accordingly, if power source voltage Vcc is again applied to respective circuits, due the level of the output signal Vout (intermediate level) of the initialization setting circuit 20a, the inverters 34 and 35 of the latch circuit 30 start operation simultaneously. As a result, it becomes possible that the potential at the output terminal B of the latch circuit 30 becomes "H" level. Therefore, the problem of malfunction can arise upon writing in and reading out data.